1. Technical Field
The invention relates to a semiconductor device for use in a semiconductor integrated circuit, and more particularly, to a pitcher-shaped active area for a field effect transistor having a widened top portion.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced without loss of device performance. Particularly, because the integration of semiconductor devices increases, there is a corresponding size reduction in field effect transistors (FETs).
FETs are the basic electrical devices of today's integrated circuits. Such transistors may be formed in conventional substrates (such as a silicon substrate), or in silicon-on-insulator (SOI) substrates for example. For example, a conventional metal oxide semiconductor field effect transistor (MOS FET) formed in a silicon substrate may include a gate oxide layer formed on the substrate, a gate formed on the gate oxide layer, spacers formed beside the gate on the gate oxide layer, and a doped source region and a doped drain region arranged on respective sides of a gate conductor in the substrate. The gate is separated from a channel (which is situated between the source and drain regions) by the gate oxide layer. Shallow trench insulator (STI), local oxidation of silicon (LOCOS), or poly-buffered LOCOS isolations are usually employed to provide for isolation of adjacent transistors.
Conventionally, in the process of fabricating a conventional FET, lithography is used to form an opening for an active area for the FET, then etching is carried out to form the actual active area for the FET in the silicon substrate. However, there are some problems associated with the conventional FET active area and the conventional method steps for forming such a FET active area. First, the top width of the active area structure of the FET is generally defined by lithography, and therefore, is limited by the smallest ground rules for exposure with a lithography tool. Second, because the top corners of the active area are angular and not rounded, the top angular corners of the active area create a higher electric field between the gate conductor and the active area, which translates into a lower threshold voltage at the angular corners than at the back of the FET.
Additionally, when the FET is operated, an electric field is generated by applying a voltage to the gate. The electrical field is used to control a channel, which is between the source region and the drain region. For example, if channel is turned on, the electrons flow from the source region to the drain region. In contrast, if the channel is turned off, the electrons cannot flow between the source region and the drain region. Therefore, the on or off state of the channel controls the connection or disconnection of the circuit. In current device designs for logic and memory devices, a high transistor on-current is essential for fast charge transfer and therefore, increased switching speed of the logic or memory device. One conventional method of increasing transistor on-current is by reducing the effective channel length by reduction of the lithographic gate length. However, his conventional method necessitates an increase in channel doping combined with source-drain engineering for highly doped shallow extensions in device design in an attempt to try and avoid transistor short-channel effects and higher serial resistance.
Thus, there is a need for an improved active area structure for a FET having an increased transistor on-current, a decreased transistor serial resistance, and a decreased contact resistance.